1. Field of the Invention
Example embodiments relate to a semiconductor memory device, and more particularly, to a method and apparatus for controlling a read latency of a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
A typical DRAM system has an external memory controller for processing a read request and/or a write request. The memory controller expects effective data to be loaded on a data bus after a number of external system clock cycles from a read request. The number of external system clock cycles may be predetermined. For example, the number of external system clock cycles may be seven. In a conventional DRAM system, the number of external system clock cycles corresponds to a read latency, which may be predetermined. The conventional DRAM typically has a clock system that receives an external clock signal. The conventional DRAM may generate internal clock signals from the external clock signal, and the internal clock signals may be used for one or more internal operations. A well-known internal clock system implemented in a DRAM is a back-timed read clock domain provided by a delay locked loop (DLL). The back-timed read clock domain provides a read clock signal. The read clock signal has a desired and/or predetermined phase relationship with an external system clock signal and is supplied to read latches. The back-timed read clock domain compensates for delay components on a data output path in order to provide read clock signals acting on output data latches to obtain a prescribed phase alignment with the external system clock signal.
FIG. 1 is a block diagram of a conventional memory device 100 and is used herein for explaining a read latency control operation of the conventional memory device 100. Referring to FIG. 1, the memory device 100 includes a command buffer 110 receiving an external command CMD and a clock buffer 120 receiving an external clock signal EXCLK. The external clock signal EXCLK buffered by the clock buffer 120 is applied to a DLL 130 to generate an internal clock signal DLLCLK of the memory device 100. The conventional memory device 100 controls a read latency in response to a read command PREAD. The read command PREAD output from the command buffer 110 is applied to a latency counter 140. The latency counter 140 samples the read command PREAD in response to the internal clock signal DLLCLK and an output clock signal of a replica delay unit 150. Based on the read command PREAD, the internal clock signal DLLCLK, and an output signal of the replica delay unit 150, the latency counter generates a latency signal LATENCY.
The replica delay unit 150 generates an internal clock signal delayed from the internal clock signal DLLCLK by a summed delay time tSAC+tREAD corresponding to the sum of a first delay time tSAC from when the internal clock signal DLLCLK is generated to when output data DOUT is output and a second delay time tREAD required for a read command to synchronize with the external clock signal EXCLK to be transmitted to the latency counter 140. The replica delay unit 150 is a replica of circuits on a first path tSAC and circuits on a second path tREAD. The DLL 130 delays the external clock signal EXCLK such that the internal clock signal DLLCLK leads the external clock signal EXCLK by the first delay tSAC.
The internal clock signal DLLCLK is applied to a delay compensator 160 and a clock signal, which is delayed from the internal clock signal DLLCLK by a delay time of the latency counter 140, is output from the delay compensator 160. A data output buffer 170 outputs the output data DOUT in response to the latency signal LATENCY and the clock signal output from the delay compensator 160.
FIG. 2A is a circuit diagram of a conventional latency counter 140a, which may be used as the latency counter 140 of FIG. 1 and a conventional replica delay unit 150. FIG. 2B is a timing diagram of the operation of the conventional latency counter 140a illustrated in FIG. 2A. Referring to FIG. 2A, the latency counter 140a is configured in the form of a shift register including first through fifth flip-flops 210, 212, 214, 216 and 218. The number of flip-flops depends on a CAS latency CL. The replica delay unit 150 includes first, second, third and fourth unit delays 202, 204, 206 and 208. The total delay time of the first, second, third and fourth unit delays 202, 204, 206 and 208 corresponds to tSAC+tREAD. A delay time tD of each of the first, second, third and fourth unit delays 202, 204, 206 and 208 corresponds to (tSAC+tREAD)/(CL−1).
In the replica delay unit 150, the internal clock signal DLLCLK is input to the first unit delay 202. First, second, third and fourth unit delays 202, 204, 206 and 208 are connected in series and the fourth unit delay 208 generates a clock signal P1 delayed from the internal clock signal DLLCLK by tSAC+tREAD, as illustrated in FIG. 2B. In the latency counter 140a, the first through fifth flip-flops 210, 212, 214, 216 and 218 receive the buffered read command PREAD and generate the latency signal LATENCY in response to output clock signals P1 through P4 of the first, second, third and fourth unit delays 202, 204, 206 and 208 and the internal clock signal P5 (DLLCLK). The latency counter 140a samples the buffered read command PREAD in response to the output clock signal P1 of the fourth unit delay 208 and generates the latency signal LATENCY from the internal clock signal P5 (DLLCLK).
The latency counter 140a configured in the form of a shift register is advantageous when the number of CAS latencies that the latency counter 140a should support is small but disadvantageous for high-speed DRAMs having a large number of CAS latencies that the latency counter 140a should support. This is at least in part because a delay chain such as the latency counter 140a must be additionally required according to CAS latency and thus, the number of delay chains increases when the number of CAS latencies increases. This requires delay time tuning in consideration of a process variation, a voltage variation and a temperature variation and increasing the number of delay chains increase a layout area of a DRAM. Furthermore, a minimum access time tAA of a DRAM is increased when the number of CAS latencies increases because of a timing margin that must be secured for each of the first through fifth flip-flops 210, 212, 214, 216 and 218, and thus the limit of the data access speed of the DRAM is determined by the latency counter rather than a speed of reading data from a memory cell.
To address and/or solve issues of the shift register type latency counter 140a, a conventional pointer type latency counter 140b as illustrated in FIG. 3A has been proposed. Referring to FIG. 3A, the conventional latency counter 140b includes two ring counters 310 and 320. The number of bits of the ring counters 310 and 320 is determined by CL. The first ring counter 310 receives an internal clock signal DLLCLK and generates a clock pulse signal TCLK<i> (i=0 through 5). The second ring counter 320 receives an internal clock signal delayed from the internal clock signal DLLCLK by tSAC+tREAD through the replica delay unit 150 and generates a clock pulse signal SCLK<i> (i=0 through 5). A delay time from when the clock pulse signal TCLK<i> is generated until when the clock pulse signal SCLK<i> is generated becomes tSAC+tREAD, and a delay time from when the clock pulse signal SCLK<i> is generated until when the clock pulse signal TCLK<i> is generated becomes N*tCK−(tSAC+tREAD). N is the number of bits of a ring counter and is generally determined by CL.
Still referring to FIG. 3A, first switches 330 sample the buffered read command PREAD in response to the pulse signal SCLK<i> and transfer the sampled read command to a register 340. Second switches 350 sample the read command PREAD stored in the register 340 in response to the pulse signal SCLK<i> to generate the latency signal LATENCY. The read command PREAD is delayed by N*tCK in the latency counter 140b when the delay time from when the internal clock signal DLLCLK is generated until when the output data DOUT is output and the delay time tREAD required for a read command synchronized with the external clock signal EXCLK to be transmitted to the latency counter 140 are considered. An example timing diagram of the operation of the conventional latency counter 140b is illustrated in FIG. 3B. In the example of FIG. 3B, the CL is six. The latency signal LATENCY is generated in synchronization with the internal clock signal DLLCLK.
The pointer type latency counter 140b does not bring about a variation in the minimum access time tAA of the DRAM even when CL is increased because the sampled read command is not shifted. However, the latency counter 140b has to maintain the delay time tSAC+tREAD between the clock pulse signal TCLK<i> and the clock pulse signal SCLK<i> for a normal latency control operation, and thus a glitch clock signal must be prevented from being input to the latency counter 140b. Furthermore, the latency counter 140b additionally requires a latency clock initialization circuit, and thus the delay time of the second ring counter 310 generating the clock pulse signals TCLK<i> is added to increase the delay time tSAC. Moreover, if the DLL 120 (illustrated in FIG. 1) cannot be powered off without using a glitch clock signal in a power down mode of a DRAM, power consumption in the power down mode is increased.